1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly relates to a semiconductor device that performs a refresh operation in response to a refresh command issued from outside.
2. Description of Related Art
DRAMs (Dynamic Random Access Memories) that are typical semiconductor devices are volatile semiconductor memory devices. In the DRAMs, because a plurality of pieces of information are stored as electric charges in capacitors that are included in a plurality of memory cells, information is lost due to a leak current if a refresh operation is not performed periodically. Therefore, it is necessary to refresh all memory cells before the information is lost due to the leakage current. A period(=tREF) of 64 milliseconds (msec) is defined as a standard for refreshing all the memory cells. Accordingly, refresh commands issued by a controller are issued in such a manner that all word lines associated with all the memory cells are selected within a period of 64 msec, for example, the refresh commands are issued for 8192(=213) times. Note that the exemplified number of 8192 times represents the number of word lines to which the plurality of memory cells are respectively connected.
As conventional techniques related to the refresh operation, techniques described in Japanese Patent Application Laid-open Nos. 2008-135113 and 2006-99877 are known. Japanese Patent Application Laid-open No. 2008-135113 discloses a semiconductor device in which refresh execution signals are generated for plural times in response to issuance of one refresh command, and a different memory bank is refreshed each time the refresh execution signals are activated. Japanese Patent Application Laid-open No. 2006-99877 discloses a semiconductor device that can specify a memory bank to be refreshed by supplying a bank address of the memory bank to a semiconductor memory device in synchronization with a refresh command.
However, the semiconductor devices disclosed in the above conventional techniques have an event such that, because the number of times of the refresh command to be issued within a period of 64 msec is fixed, there is less flexibility in terms of control performed by a controller.
The above event is not limited to DRAMs, and the event generally occurs to every semiconductor device that requires a refresh operation due to its memory cell configuration.
In one embodiment, there is provided a semiconductor device that includes a refresh control circuit that generates a refresh execution signal in response to a refresh command issued from outside; a refresh address counter that updates a refresh address in response to the refresh execution signal; and a first circuit that receives the refresh command and a first signal, the first signal supplied from outside in synchronization with the refresh command, and generates a refresh-mode specifying signal based on the refresh command and the first signal, and outputs a refresh-mode specifying signal to the refresh control circuit, wherein the refresh control circuit generates the refresh execution signal 2n times each time when the refresh command is issued, where n is an integer equal to or larger than 0 and equal to or less than k, and the refresh control circuit changes a value of n based on the refresh-mode specifying signal.
In another embodiment, there is provided a semiconductor device that includes a refresh control circuit that generates a refresh execution signal in response to a refresh command issued from outside; and a memory cell array including a plurality of memory cells that are refreshed in response to the refresh execution signal, wherein the refresh control circuit generates the refresh execution signal 2n times each time when the refresh command is issued, when number of times the refresh command is issued in a predetermined period is 2m+k−n, where m is a natural number and n is an integer equal to or larger than 0 and equal to or less than k.
According to the present invention, because the frequency of generation of a refresh execution signal in response to input of one refresh command can be changed dynamically, flexible control can be performed by a controller.